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LTC1325 Microprocessor-Controlled Battery Management System
FEATURES
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DESCRIPTION
The LTC(R)1325 provides the core of a flexible, cost-effective solution for an integrated battery management system. The monolithic CMOS chip controls the fast charging of nickel-cadmium, nickel-metal-hydride, lead-acid or lithium batteries under microprocessor control. The device features a programmable 111kHz PWM constant current source controller with built-in FET driver, 10-bit ADC, internal voltage regulator, discharge-before-charge controller, programmable battery voltage attenuator and an easy-to-use serial interface. The chip may operate in one of five modes: power shutdown, idle, discharge, charge or gas gauge. In power shutdown the supply current drops to 30A and in the idle mode, an ADC reading may be made without any switching noise affecting the accuracy of the measurement. In the discharge mode, the battery is discharged by an external transistor while the battery is being monitored by the LTC1325 for fault conditions. The charge mode is terminated by the P while monitoring any combination of battery voltage and temperature, ambient temperature and charge time. The LTC1325 also monitors the battery for fault conditions before and during charging. In the gas gauge mode the LTC1325 allows the total charge leaving the battery to be calculated.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Fast Charge Nickel-Cadmium, Nickel-Metal-Hydride, Lithium Ion or Lead-Acid Batteries under P Control Flexible Current Regulation: - Programmable 111kHz PWM Current Regulator with Built-In PFET Driver - PFET Current Gating for Use with External Current Regulator or Current Limited Transformer Discharge Mode Measures Battery Voltage, Battery Temperature and Ambient Temperature with Internal 10-Bit ADC Battery Voltage, Temperature and Charge Time Fault Protection Built-In Voltage Regulator and Programmable Battery Attenuator Easy-to-Use 3- or 4-Wire Serial P Interface Accurate Gas Gauge Function Wide Supply Range: VDD = 4.5V to 16V Can Charge Batteries with Voltages Greater Than VDD Can Charge Batteries from Charging Supplies Greater Than VDD Digital Input Pins Are High Impedance in Shutdown Mode
APPLICATIONS
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System Integrated Battery Charger
TYPICAL APPLICATION
Battery Charger for up to 8 NiCd or NiMH Cells
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C2 10F P1 IRF9730 D1 1N6818
LTC1325 MPU (e.g. 8051) p1.4 p1.3 p1.2 R1
+
CREG 4.7F
1 2 3 4 5 6 7
REG DOUT DIN CS CLK LTF MCV HTF GND
VDD PGATE DIS VBAT TBAT TAMB VIN SENSE FILTER
18 17 16 15 14 13 12 11 10 CF 1F 100
R13 R5
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C1 0.1F CREG 22F THERM 2
THERM 1
R2
8 9
R3 R4
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VDD 4.5V TO 16V
L1 62H
RTRK
RDIS BAT N1 IRFZ34
RSENSE
LTC1325 * TA01
1
LTC1325
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW REG 1 DOUT 2 DIN 3 CS 4 CLK 5 LTF 6 MCV 7 HTF 8 GND 9 N PACKAGE 18-LEAD PDIP 18 VDD 17 PGATE 16 DIS 15 VBAT 14 TBAT 13 TAMB 12 VIN 11 SENSE 10 FILTER SW PACKAGE 18-LEAD PLASTIC SO WIDE
VDD to GND ............................................................. 17V All Other Pins ................................ - 0.3V to VDD + 0.3V Operating Temperature Range ..................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1325CN LTC1325CSW
TJMAX = 125C, JA = 75C/ W (N) TJMAX = 125C, JA = 100C/ W (SW)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL VDD IDD IPD VREG LDREG LIREG TCREG VDAC PARAMETER VDD Supply Voltage VDD Supply Current VDD Supply Current Regulator Output Voltage Regulator Load Regulation Regulator Line Regulation Regulator Output Tempco DAC Output Voltage CONDITIONS
VDD = 12V 5%, TA = 25C, unless otherwise noted.
q
MIN 4.5
TYP 1200 30 3.072 -1 - 60 50 160 55 34 18 20 10 50 100
VHYST VOS VBATR VBATP VEDV VLTF, VMCV VHTF AGG VOS(GG) RF TOLBATD VIL VIH IIL IIH
Fault Comparator Hysteresis Fault Comparator Offset VBAT for BATR = 1 VBAT for BATP = 1 Internal EDV Voltage LTF, MCV Voltage Range HTF Voltage Range Gas Gauge Gain Gas Gauge Offset Internal Filter Resistor Battery Divider Tolerance Input Low Voltage Input High Voltage Low Level Input Current High Level Input Current
All TTL Inputs = 0V or 5V, No Load on REG Power-Down Mode, All TTL Inputs = 0V or 5V No Load Sourcing Only, IREG = 0mA to 2mA No Load, VDD = 4.5V to 16V No Load, 0C < TA < 70C VR1 = 1, VR0 = 1, 100% Duty Ratio, ICHRG = I (Note 7) VR1 = 1, VR0 = 0, 100% Duty Ratio, ICHRG = I/3 VR1 = 0, VR0 = 1, 100% Duty Ratio, ICHRG = I/5 VR1 = 0, VR0 = 0, 100% Duty Ratio, ICHRG = I/10 VHTF = 1V, VEDV = 0.9V, VBATR = 100mV VMCV = VLTF = 2V VHTF = 1V, VEDV = 0.9V, VBATR = 100mV VMCV = VLTF = 2V
q q q
3.047
MAX 16 2000 50 3.097 -5 - 100 180 62 38 21
140 48 30 16
UNITS V A A V mV/mA V/V ppm/C mV mV mV mV mV mV mV mV V mV V V LSB % V V A A
q q
VDD - 1.8 860 1.6 0.5
900
945 2.8 1.3
- 0.4V < VSENSE < 0V - 0.4V < VSENSE < 0V (Note 6) All Division Ratios CLK, CS, DIN CLK, CS, DIN VCLK, VCS or VDIN = 0V VCLK, VCS or VDIN = 5V
q q q q q
-4 1 1000 -2 0.8 - 2.5 - 2.5 2 1.3 1.7 2.4 2.5 2.5
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LTC1325
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VOL Output Low Voltage VOH Output High Voltage IOZ Hi-Z Output Leakage VOHFET DIS or PGATE Output High VOLFET DIS or PGATE Output Low tdDO Delay Time, CLK to DOUT Valid tdis Delay Time, CS to DOUT Hi-Z ten Delay Time, CLK to DOUT Enabled thDO Time DOUT Remains Valid After CLK trDOUT DOUT Rise Time tfDOUT DOUT Fall Time fCLK Serial I/O Clock Frequency trPGATE PGATE Rise Time tfPGATE PGATE Fall Time fOSC Internal Oscillator Frequency A/D Converter Offset Error Linearity Error Full-Scale Error On-Channel Leakage Off-Channel Leakage
VDD = 12V 5%, TA = 25C, unless otherwise noted.
MIN
q q q q q q q q q q q q q q
CONDITIONS DOUT, IOUT = 1.6mA DOUT, IOUT = - 1.6mA VCS = 5V VDD = 4.5V to 16V VDD = 4.5V to 16V See Test Circuits See Test Circuits See Test Circuits See Test Circuits See Test Circuits See Test Circuits CLK Pin CLOAD = 1500pF CLOAD = 1500pF Charge Mode, Fail-Safes Disabled VIN Channel (Note 3) VIN Channel (Notes 3, 4) VIN Channel (Note 3) VIN Channel ON Only (Notes 3, 5) VIN Channel OFF (Notes 3, 5)
TYP
MAX 0.4 10
2.4 VDD - 0.05 0.05 650 510 400 30 250 100 500 150 150 130 2 0.5 1 10 10
25
90
q q q q q
111
UNITS V V A V V ns ns ns ns ns ns kHz ns ns kHz LSB LSB LSB A A
RECO
SYMBOL thDI tdsuCS tdsuDI tWHCLK tWLCLK tWHCS tWLCS
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to the GND pin. Note 3: VREG within specified min and max limits, CLK (Pin 5) = 500kHz, unless otherwise stated. ADC clock is the serial CLK.
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E DED CHARACTERISTICS
CONDITIONS MIN 150 1 400 0.8 1 1 43 52 TYP MAX UNITS ns s ns s s s CLK Cycles CLK Cycles
PARAMETER Hold Time, DIN After CLK Setup Time, CS Before First CLK Setup Time, DIN Stable Before First CLK CLK High Time CLK Low Time CS High Time Between Data Transfers CS Low Time During Data Transfer
MSBF = 1 MSBF = 0
Note 4: Linearity error is specified between the actual end points of the A/D transfer curve. Note 5: Channel leakage is measured after channel selection. Note 6: Gas gauge offset excludes A/D offset error. Note 7: I = VDAC(Duty Ratio)/RSENSE, where VDAC is the DAC output voltage with control bits VR1 = VR0 = 1, duty ratio = 1 and RSENSE is determined by the user.
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LTC1325 TYPICAL PERFORMANCE CHARACTERISTICS
Regulator Output Voltage vs Load Current
3.077 TA = 27C
REGULATOR OUTPUT VOLTAGE (V)
3.076 3.075 3.074
VDD = 12V VDD = 4.5V
3.079 3.078 3.077 3.076 3.075 3.074 3.073 3.072 0 10
VDD = 16V VDD = 12V
VDD SUPPLY CURRENT (A)
VDD = 16V
REGULATOR OUTPUT VOLTAGE (V)
3.073 3.072 3.071 3.070 0 0.5 1.0 3.0 3.5 LOAD CURRENT (mA) 1.5 2.0 2.5 4.0
Charge Current vs Battery Voltage
160 VR1 = 1, VR0 = 1 140
DAC OUTPUT VOLTAGE (mV)
CHARGE CURRENT (mA)
120 100 80 60 40 20 0 0
VDD = 12V, RSENSE = 1, L = 100H, P1: IRF9531
120 100 80 60 40 20 0 VR1 = 1, VR0 = 0 VR1 = 0, VR0 = 1 VR1 = 0, VR0 = 0 0 10 40 30 50 20 TEMPERATURE (C) 60 70 VDD = 12V
SHUTDOWN CURRENT (A)
VR1 = 1, VR0 = 0 VR1 = 0, VR0 = 1
VR1 = 0, VR0 = 0 2 4 6 8 BATTERY VOLTAGE (V) 10 12
1325 G04
Fault Comparator Threshold vs Temperature
1.0
FAULT COMPARATOR THRESHOLD (V)
FAULT COMPARATOR THRESHOLD (V)
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10
VCELL FOR EDV = HIGH
10 9 8 7 6 5 4 3 2 1 0
VBAT FOR BATP = HIGH, VDD = 12V
GAS GAUGE GAIN AND OFFSET (COUNTS)
VTBAT FOR HTF = HIGH, VHTF = 0.4V
VCELL FOR BATR = HIGH
20
30 40 50 60 TEMPERATURE (C)
4
UW
70
1325 G07
Regulator Output Voltage vs Temperature
3.082 3.081 3.080 IREG = 0 1000 900 800 700 600 500 400 300 200 100 20 30 40 50 60 70 TEMPERATURE (C) 80 90 0
VDD Supply Current vs Temperature
VDD = 16V
VDD = 4.5V VDD = 12V
VDD = 4.5V
0
10
20
30 40 50 60 70 TEMPERATURE (C)
80
90
1325 G01
1325 G02
1325 G03
DAC Output Voltage vs Temperature
180 160 140 VR1 = 1, VR0 = 1
20 25
Shutdown Current vs Temperature
VDD = 16V
15 VDD = 12V 10
5 VDD = 4.5V 0 0 10 20 30 40 50 60 70 TEMPERATURE (C) 80 90
1325 G05
1325 G06
Fault Comparator Threshold vs Temperature
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Gas Gauge Gain and Offset vs Temperature
0 - 0.5 -1.0 -1.5 -2.0 -2.5 -3.0 - 3.5 GAS GAUGE GAIN -4.0 -4.5 0 10 20 30 40 50 60 TEMPERATURE (C) 70 80 GAS GAUGE OFFSET VSENSE = -0.2V AND - 0.4V INCLUDES CHANGES IN VREG WITH TEMPERATURE
VCELL FOR MCV = HIGH, VMCV = 2.8V AND VTBAT FOR LTF = HIGH, VLTF = 2.8V VCELL FOR MCV = HIGH, VMCV = 1.6V VTBAT FOR LTF = HIGH, VLTF = 1.6V VTBAT FOR HTF = HIGH, VHTF = 1.35V 70
80
10
20
30 40 50 60 TEMPERATURE (C)
80
1325 G08
1325 G09
LTC1325 TYPICAL PERFORMANCE CHARACTERISTICS
PGATE Rise Time vs Load Capacitance
1200 1000 1000
DIFFERENTIAL NONLINEARITY (LSB)
PGATE RISE TIME (ns)
800 600 400 200 0 0 2 4
TA = 27C TA = 70C
PGATE FALL TIME (ns)
TA = 0C
6 8 10 12 14 16 18 20 LOAD CAPACITANCE (nF)
1325 G10
Discharge Rise and Fall Time vs Load Capacitance
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DISCHARGE RISE AND FALL TIME (s)
MINIMUM CHARGE VOLTAGE (V)
RISE TIME
10 8 6 FALL TIME 4 2 0 0 2 4 6 8 10 12 14 16 18 20 LOAD CAPACITANCE (nF)
1325 G13
12 10 8 6 4 2 0 1 2 3 4 5 6 7 8
1325 G14
INTEGRAL NONLINEARITY (LSB)
12
TA = 70C TA = 27C TA = 0C
Oscillator Frequency vs Temperature
118 500
CLK TO DOUT ENABLE DELAY TIME (ns)
CLK TO DOUT VALID DELAY TIME (ns)
117
OSCILLATOR FREQUENCY (kHz)
116 115 114 113 112 111 110 109 108 -40 -20 40 20 0 60 TEMPERATURE (C) 80 100
UW
1325 G16
PGATE Fall Time vs Load Capacitance
1.0
Differential Nonlinearity
VDD = 12V fCLK = 500kHz 0.5
900 800 700 600 500 400 300 200 100 0 0 2 4 6 8 10 12 14 16 18 20 LOAD CAPACITANCE (nF)
LTC1325 G11
TA = 27C
TA = 70C
0
TA = 0C
-0.5
-1.0
0
128 256 384 512 640 768 896 1024 CODE
1325 G12
Minimum Charging Supply vs Number of Cells
16 14 RSENSE = 0.15, VR1 = 1,VR0 = 1 L = 10H TO 100H IRF9Z30PFET, 1N5819 DIODE
Integral Nonlinearity
1.0 VDD = 12V fCLK = 500kHz 0.5
0
RSENSE = 1, VR1 = 1, VR0 = 1 L = 25H TO 100H IRF9Z30PFET, 1N5819 DIODE TA = 27C, NiCd BATTERIES VCELL = 1.4V NOMINAL
-0.5
-1.0
0
NUMBER OF CELLS
128 256 384 512 640 768 896 1024 CODE
1325 G15
CLK to DOUT Enable Delay Time vs Temperature
700 600 500 400 300 200 100 0
0 10 20 30 40 50 60 TEMPERATURE (C) 70 80 450 400 350 300 250 200 150 100 50 0
CLK to DOUT Valid Delay Time vs Temperature
DOUT GOING HIGH DOUT GOING LOW
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
1325 G17
1325 G18
5
LTC1325
PIN FUNCTIONS
REG (Pin 1): Internal Regulator Output. The regulator provides a steady 3.072V to the internal analog circuitry and provides a temperature stable reference voltage for generating MCV, HTF, LTF and thermistor bias voltages with external resistors. Requires a 4.7F or greater bypass capacitor to ground. DOUT (Pin 2): TTL Data Output Signal for the Serial Interface. DOUT and DIN may be tied together to form a 3-wire interface, or remain separated to form a 4-wire interface. Data is transmitted on the falling edge of CLK (Pin 5). DIN (Pin 3): TTL Data Input Signal for the Serial Interface. The data is latched into the chip on the rising edge of the CLK (Pin 5). CS (Pin 4): TTL Chip Select Signal for the Serial Interface. CLK (Pin 5): TTL Clock for the Serial Interface. LTF (Pin 6): Minimum Allowable Battery Temperature Analog Input. LTF may be generated by a resistive divider between REG (Pin 1) and ground. MCV (Pin 7): Maximum Allowable Cell Voltage Analog Input. MCV may be generated by a resistive divider between REG (Pin 1) and ground. HTF (Pin 8): Maximum Allowable Battery Temperature Analog Input. HTF may be generated by a resistive divider between REG (Pin 1) and ground. GND (Pin 9): Ground. FILTER (Pin 10): The external filter capacitor CF is connected to this pin. The filter capacitor is connected to the output of the internal resistive divider across the battery to reduce the switching noise while charging. In the gas gauge mode, CF along with an internal RF = 1k form a lowpass filter to average the voltage across the sense resistor. SENSE (Pin 11): The Sense pin controls the switching of the 111kHz PWM constant current source in the charging mode. The Sense pin is connected to an external sense resistor RSENSE and the negative side of the battery. The charging loop forces the average voltage at the Sense pin to equal a programmable internal reference voltage VDAC. The battery charging current is equal to VDAC/RSENSE. In the gas gauge mode the voltage across the Sense pin is filtered by an RC network (RF and CF), amplified by an inverting gain of four, then multiplexed to the ADC so the average discharge current through the battery may be measured and the total charge leaving the battery calculated. VIN (Pin 12): General Purpose ADC Input. TAMB (Pin 13): Ambient Temperature Input. Connect to an external thermistor network. Tie to REG if not used. May be used as another general purpose ADC input. TBAT (Pin 14): Battery Temperature Input. Connect to an external NTC thermistor network. Tie to REG if not used. VBAT (Pin 15): Battery Input. An internal voltage divider is connected between the VBAT and Sense pins to normalize all battery measurements to one cell voltage. The divider is programmable to the following ratios: 1/1, 1/2, 1/3 . . . 1/15, 1/16. In shutdown and gas gauge modes the divider is disconnected. DIS (Pin 16): Active High Discharge Control Pin. Used to turn on an external transistor which discharges the battery. PGATE (Pin 17): FET Driver Output. Swings from GND to VDD. VDD (Pin 18): Positive Supply Voltage. 4.5V < VDD < 16V.
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LTC1325
BLOCK DIAGRAM
VDD 18 5V DIGITAL REGULATOR DIGITAL INPUT CIRCUITS 3.072V ANALOG REGULATOR
GND
9
CLK CS DIN DOUT
5 4 3 2 10 2 SERIAL I/O
10-BIT A/D CONVERTER
DIVIDER TOUT TIMEOUT LOGIC 3 TO0 TO TO2
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
1.4V
DOUT 100pF
LTC1325 * TC01
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PS 1 ANALOG AND DIGITAL VDD ADC REFERENCE t OUT REG 16 DIS BATP, BATR, FMCV, FEDV, FHTF, FLTF, t OUT 7 CONTROL LOGIC MOD0 TO MOD1, PS 3 FAULT DETECT CIRCUITRY 6 8 7 LTF HTF MCV PS, MSBF 3 DS0 TO DS1 SGL/DIFF 12 13 14 DIV0 TO DIV3 4 ADC MUX 15 VIN TAMB TBAT VBAT 5 GAS GAUGE MOD0 TO MOD1, VR0 TO VR1, PS CHARGE 11 10 17 111kHz OSCILLATOR PS CHARGE LOOP AND GAS GAUGE 3 SENSE FILTER PGATE DR0 TO DR3 DUTY RATIO GENERATOR
LTC1325 * BD
Load Circuit for tdis and ten
TEST POINT
3k
3k DOUT 100pF
5V tdis WAVEFORM 2, ten tdis WAVEFORM 1
LTC1325 * TC02
7
LTC1325
TEST CIRCUITS
Voltage Waveforms for DOUT Delay Time, tdDO Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
2.4V
CLK
0.8V tdDO 2.4V
tr tf
LTC1325 * TC04
0.4V
DOUT 0.4V
LTC1325 * TC03
On and Off Channel Leakage
3.072V ION
CS
Voltage Waveforms for tdis
2V
A IOFF A
ON CHANNEL
DOUT WAVEFORM 1 (SEE NOTE 1) tdis DOUT WAVEFORM 2 (SEE NOTE 2)
90%
} OFF CHANNELS
10%
NOTE: EXTERNAL CHANNELS ONLY-- TBAT, TAMB AND VIN
LTC1325 * TC05
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY CS. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS LTC1325 * TC06 SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY CS.
Voltage Waveforms for ten
CS
DIN
START VR1
CLK
1
21
22 ten
23
0.4V
24
DOUT
THREE-STATE
NULL 0.4V
D9
LTC1325 * TC07
8
LTC1325 TI I G DIAGRA
MSB-FIRST DATA (MSBF = 1) CS CLK START DIN DOUT HI-Z COMMAND WORD NULL D9 ADC DATA BATP D1 D0 STATUS WORD FS HI-Z MSBF
MSB-FIRST DATA (MSBF = 0) CS CLK START DIN DOUT HI-Z COMMAND WORD NOTE: THE TIMING DIAGRAM SHOWS TWO POSSIBLE COMMAND WORDS. REFER TO FUNCTIONAL DESCRIPTION FOR INFORMATION ON HOW TO CONSTRUCT THE COMMAND WORD NULL D9 D1 D0 D1 ADC DATA BATP D9 STATUS WORD FS HI-Z
LTC1325 * TD
FUNCTIONAL DESCRIPTIO
GENERAL DESCRIPTION
During normal operation, a command word is shifted into the chip via the serial interface, then an ADC measurement is made and the 10-bit reading and chip status word are shifted out. The command word configures the LTC1325 and forces it into one of five modes: power shutdown, idle, discharge, charge or gas gauge mode. In the power shutdown mode, the analog section is turned off and the supply current drops to 30A. The voltage regulator, which provides power to the internal analog circuitry and external bias networks, is shut down. The voltage divider across the battery is disconnected and only the voltage regulator for the serial interface logic is left on. During the idle mode, the chip is fully powered but the discharge, charge, and gas gauge circuits are off. The chip may be placed in the idle mode momentarily while charging the battery, allowing an ADC measurement to be made without any switching noise from the PWM current source affecting the accuracy of the reading. The mode command bits are picked off as they appear at DIN, allowing the charging loop to turn off and settle while the remainder of the command word is being shifted in.
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During the discharge mode, the battery is discharged by an external transistor and series resistor. The battery is monitored for fault conditions. In the charge mode, the P monitors the battery's voltage, temperature and ambient temperature via the 10-bit ADC. Termination methods such as -VBAT, VBAT/Time, TBAT, TBAT/Time, (TBAT - TA), maximum temperature, maximum voltage and maximum charge time may be accurately implemented in software. The LTC1325 also monitors the battery for fault conditions. In the gas gauge mode, the average voltage across the sense resistor can be measured to determine the average battery load current. The sense voltage is filtered by an RC circuit, multiplied by an inverting gain of four, then converted by the ADC. The P can then accumulate the ADC measurements and do a time average to determine the total charge leaving the battery. The RC circuit consists of an internal 1k resistor RF and an external capacitor CF connected to the Filter pin.
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LTC1325
FUNCTIONAL DESCRIPTIO
COMMAND WORD The command word is 22 bits long and contains all the information needed to configure and control the chip. On power-up all bits are cleared to logical "0."
1 2 3 4 SGL/ DIFF 12 DIV3 20 TO2 5 MSBF 13 PS 21 VR0 6 DS0 14 DR0 22 VR1
LTC1325 * F01
7 DS1 15 DR1
START MOD0 MOD1 =1 9 DIV0 17 FSCLR 10 DIV1 18 TO0 11 DIV2 19 TO1
Figure 1. Command Word
Bit 1: Start Bit (Start) The first "logical one" clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer and all leading zeros which precede this logical one will be ignored. After the start bit is received, the remaining bits of the command word will be clocked in. Bits 2 and 3: Mode Select (MOD0 and MOD1) The two mode bits determine which of four modes the chip will be in: idle, discharge, charge or gas gauge.
MOD1 0 0 1 1 MOD0 0 1 0 1 DESCRIPTION Idle Discharge Charge Gas Gauge
Bit 4: Single-Ended Differential Conversion (SGL/DIFF) SGL/DIFF determines whether the ADC makes a singleended measurement with respect to ground or a differential measurement with respect to the Sense pin.
SGL/DIFF 0 1 DESCRIPTION Single-Ended ADC Conversion Differential ADC Conversion (with respect to Sense)
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Bit 5: MSB-First/LSB-First (MSBF) The ADC data is programmed for MSB-first or LSB-first sequence using the MSBF bit. See Serial I/O description for details.
MSBF 0 1 DESCRIPTION LSB-First Data Follows MSB-First Data MSB-First Data Only
8 DS2 16 DR2
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Bits 6 to 8: ADC Data Input Select (DS0 to DS2) DS2, DS1 and DS0 select which circuit is connected to the ADC input. Do not use unlisted combinations.
DS2 0 0 0 0 1 DS1 0 0 1 1 0 DS0 0 1 0 1 0 DESCRIPTION Gas Gauge Output Battery Temperature Pin, TBAT Ambient Temperature Pin, TAMB Battery Divider Output Voltage, VCELL VIN Pin
Bits 9 to 12: Battery Divider Ratio Select (DIV0 to DIV3) DIV3, DIV2, DIV1 and DIV0 select the division ratio for the voltage divider across the battery.
DIV3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DIV2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DIV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DIV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DESCRIPTION (VBAT - VSENSE)/1 (VBAT - VSENSE)/2 (VBAT - VSENSE)/3 (VBAT - VSENSE)/4 (VBAT - VSENSE)/5 (VBAT - VSENSE)/6 (VBAT - VSENSE)/7 (VBAT - VSENSE)/8 (VBAT - VSENSE)/9 (VBAT - VSENSE)/10 (VBAT - VSENSE)/11 (VBAT - VSENSE)/12 (VBAT - VSENSE)/13 (VBAT - VSENSE)/14 (VBAT - VSENSE)/15 (VBAT - VSENSE)/16
LTC1325
FUNCTIONAL DESCRIPTIO
Bit 13: Power Shutdown (PS) PS selects between the normal operating mode, or the shutdown mode.
PS 0 1 DESCRIPTION Normal Operation Shutdown All Circuits Except Digital Inputs
Bits 14 to 16: Duty Ratio Select (DR0 to DR2) DR2, DR1 and DR0 select the duty cycle of the charging loop operation (not 111kHz PWM duty cycle). The last three selections place the chip into a test mode and should not be used.
DR2 0 0 0 0 1 1 1 1 DR1 0 0 1 1 0 0 1 1 DR0 0 1 0 1 0 1 0 1 DESCRIPTION 1/16 1/8 1/4 1/2 1 Test Mode 1 Test Mode 2 Test Mode 3
Bit 17: Fail-Safe Latch Clear (FSCLR) When FSCLR bit is set to one, the internal fail-safe timer is reset to 0, and the fail-safe latches are reset. FSCLR is automatically reset to 0 when CS goes high.
FSCLR 0 1 DESCRIPTION No Action Reset Fail-Safe Timer and Latches
Bits 18 to 20: Timeout Period Select (TO0 to TO2) TO2, TO1 and TO0 select the desired fail-safe timeout period,tOUT. On power-up, the default timeout is 5 minutes.
TO2 0 0 0 0 1 1 1 1 TO1 0 0 1 1 0 0 1 1 TO0 0 1 0 1 0 1 0 1 TIMEOUT (MINUTES) 5 10 20 40 80 160 320 Indefinite (No Timeout)
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Bits 21 and 22: Charging Loop Reference Voltage Select (VR0 and VR1) VR1 and VR0 select the desired reference voltage VCHRG for the charging loop. The charging loop will force the average voltage at the Sense pin to be equal to VDAC. The average charging current is VDAC/RSENSE (see Figure 4).
VR1 0 0 1 1 VR0 0 1 0 1 VDAC (mV) 18 34 55 160
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STATUS WORD The status word is 8 bits long and contains the status of the internal fail-safe circuits.
1 BATP 2 BATR 3 FMCV 4 FEDV 5 FHTF 6 FLTF 7 t OUT 8 FS
LTC1325 * F02
Figure 2. Status Word
Bit 1: Battery Present (BATP) The BATP bit = 1 indicates the presence of the battery. The bit is set to 1 when the voltage at the VBAT pin falls below (VDD - 1.8V). BATP = 0 when the battery is removed and VBAT is pulled high by RTRK (see Figure 3).
BATP 0 1 CONDITIONS (VDD - 1.8) < VBAT < VDD VBAT < (VDD - 1.8)
Bit 2: Battery Reversed (BATR) or Shorted The BATR bit indicates when the battery is connected backwards or shorted. The bit is set when the battery cell voltage at the output of the battery divider VCELL is below 100mV.
BATR 0 1 CONDITIONS VCELL > 100mV VCELL < 100mV
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LTC1325
FUNCTIONAL DESCRIPTIO
Bit 3: Maximum Cell Voltage (FMCV) The MCV bit indicates when the battery cell voltage has exceeded the preset limit. The bit is set when VCELL is greater than the voltage at the MCV pin.
FMCV 0 1 CONDITIONS VCELL < VMCV VCELL > VMCV
Bit 4: End Discharge Voltage (FEDV) The EDV bit indicates when the battery cell voltage has dropped below an internally preset limit. The bit is set when the battery cell voltage at the output of the voltage divider VCELL is less than 900mV.
FEDV 0 1 CONDITIONS VCELL > 900mV VCELL < 900mV
Bit 5: High Temperature Fault (FHTF) The HTF bit indicates when the battery temperature is too high. Using a negative TC thermistor, the bit is set when the voltage at the TBAT pin is less than the voltage at the HTF pin.
FHTF 0 1 CONDITIONS TBAT > VHTF TBAT < VHTF
Bit 6: Low Temperature Fault (FLTF) The LTF bit indicates when the battery temperature is too low. Using a negative TC thermistor, the bit is set when the voltage at the TBAT pin is greater than the voltage at the LTF pin.
FLTF 0 1 CONDITIONS TBAT < VLTF TBAT > VLTF
Bit 7: Timeout (tOUT) The t OUT bit indicates that the battery charging time has exceeded the preset limit. The bit is set when the internal timer exceeds the limit set by the command bits TO0, TO1 and TO2.
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TOUT 0 1 CONDITIONS No Timeout Has Occurred Timeout Has Occurred
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Bit 8: Fail-Safe Occurred (FS) The FS bit indicates that one of the fault detection circuits halted the discharging or charging cycle. The bit is set when an EDV, LTF, HTF, or t OUT fault occurs during discharge. During charging, the bit is set when a MCV, LTF, HTF, or t OUT fault occurs. The bit is reset by the command word bit FSCLR.
FS 0 1 CONDITIONS No Fail-Safe Has Occurred Fail-Safe Has Occurred
DETAILED DESCRIPTION Fault Conditions The LTC1325 monitors the battery for fault conditions before and during discharge and charge (see Figure 3). They include: battery removed/present (BATP), battery reversed/shorted (BATR), maximum cell voltage exceeded
VDD VDD 1.8V C1 BATP RTRK
+ -
3.072V LINEAR REGULATOR
REG
+ -
PROGRAMMABLE BATTERY DIVIDER
VBAT
R1 R2
C2 FMCV
+ -
SENSE REG MCV
C3 FEDV C4 BATR C5 FHTF C6 FLTF
+ - + - - + + -
900mV R3 100mV RL
TBAT HTF R4 LTF
LTC1325 * F03
RT
Figure 3. Fail-Safe or Fault Detection Circuitry
LTC1325
FUNCTIONAL DESCRIPTIO
(MCV), minimum cell voltage exceeded (EDV), high temperature limit exceeded (HTF), low temperature limit exceeded (LTF) and time limit exceeded (tOUT). When a fault condition occurs, the discharge and charge loops are disabled or prevented from turning on and the fail-safe bit (FS) is set. The chip is reset by shifting in a new command word with the fail-safe clear FSCLR bit set. The 8-bit status word contains the state of each fault condition. Power Shutdown Mode Command: MOD1 = X, MOD0 = X, PS = 1 Status: BATP = X, BATR = X, FMCV = X, FEDV = X, FHTF = X, FLTF = X, tOUT = X
In the power shutdown mode, the analog section is turned off and the supply current drops to 30A. The voltage regulator, which provides power to the internal analog circuitry and external bias networks, is shut down. The voltage divider across the battery is disconnected and the only circuit left on is the voltage regulator for the serial interface logic. Idle Mode Command: MOD1 = 0, MOD0 = 0, PS = 0 Status: BATP = X, BATR = X, FMCV = X, FEDV = X, FHTF = X, FLTF = X, tOUT = X
The chip enters the idle mode when the proper mode command bits are set and the power shutdown command bit is cleared. During the idle mode, the chip is fully powered, but the discharge, charge and gas gauge circuits are off. The chip may be placed in the idle mode momentarily while charging the battery, allowing an ADC measurement to be made without any switching noise from the PWM current source affecting the accuracy of the reading. The mode command bits are picked off as they appear at DIN, so that while the rest of the command word is being shifted in, the charging loop has time to settle before an ADC measurement is made. Discharge Mode Command: MOD1 = 0, MOD0 = 1, PS = 0 Status: BATP = 1, BATR = 0, FMCV = X, FEDV = 0, FHTF = 0, FLTF = 0, tOUT = 0
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The chip enters the discharge mode when the proper mode command bits are set and the power shutdown command bit is clear. If a fault condition does not exist, then the DIS pin is pulled up to VDD by the internal driver. The DIS voltage is used to turn on an external transistor which discharges the battery through an external series resistor RDIS. Discharging will continue until a new command word is input to change the mode or a fault condition occurs. Charge Mode Command: MOD1 = 1, MOD0 = 0, PS = 0 Status: BATP = 1, BATR = 0, FMCV = 0, FEDV = X, FHTF = 0, FLTF = 0, tOUT = 0 The chip enters the charge mode when the proper mode command bits are set and the power shutdown command bit is clear. If a fault condition does not exist then charging can begin. Charging will continue until a new command word is input to change the mode or a fault condition occurs. The charge current may be regulated by a programmable 111kHz PWM buck current regulator, or by using the PFET to gate an external current regulator or current limited transformer. 111kHz PWM Controller The block diagram of the charging loop connected as a PWM buck current regulator is shown in Figure 4. The PWM may operate in either continuous or discontinuous mode. The loop forces the average voltage across the sense resistor to be equal to the voltage at the output of the DAC, so that the charging current becomes VDAC/RSENSE. With switch S2 on and the others off, amplifier A1 along with C1, R1 and R2 are configured as an integrator with 16kHz bandwidth. The output of the integrator is the average difference between the voltage across the sense resistor and the DAC output voltage. The rising edge of the oscillator waveform triggers the one shot which sets the flip-flop output high. This turns on the external PFET P1 by pulling its gate low via the FET driver. With P1 on, the current through the inductor L1 starts to
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LTC1325
FUNCTIONAL DESCRIPTIO
CHARGE
DR0 TO DR2
3
DUTY RATIO GENERATOR
111kHz OSCILLATOR GG ONE SHOT S1 Q S C1 16pF R1 500k S2 S3 R2 125k RF 1k S4
+
R A2
TO ADC MUX GG VR1 VR0 DAC VOLTAGE 0 0 0 18mV 0 0 1 34mV 0 1 0 55mV 0 1 1 160mV 1 X X 0mV
A1
Figure 4. Charging Loop Block Diagram
rise as does the voltage across the sense resistor. When the voltage across the sense resistor is greater than the output of the integrator, comparator A2 changes state. This resets the flip-flop and P1 is turned off. Catch diode D1 clamps the drain of P1 one diode drop below ground when the inductor flies back and the current through the inductor starts to drop. The voltage across the sense resistor also drops and may reach zero and stay there until the next clock cycle begins. The average charging current is set by the output of the DAC (VDAC) and the duty ratio generator. VDAC can be programmed to one of four values with the following ratios: 1, 1/3, 1/5 or 1/10. The duty ratio can be set to 1/16, 1/8, 1/4, 1/2 or 1. When the duty ratio is 1, the duty ratio generator output is always low and the charge loop operates continuously (see Figure 4). At other duty ratio settings, the duty generator output is a square wave with a period of 42 seconds. The time for which the generator output is low varies with the duty ratio setting. For ex-
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VDD 4.5V TO 16V PGATE P1 IRF9Z30 D1 1N5818 RDIS BATTERY SENSE CF FILTER RSENSE N1 IRFZ34 RTRK DISCHARGE DIS L1 REG 3.072V VDAC DAC 2 VR0, VR1 GG CHIP (GAS GAUGE) BOUNDARY
LTC1325 * F04
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ample, if a duty ratio of 1/2 is programmed, the generator output is low only for 42/2 = 21 seconds. Since the loop operates for only 21 out of every 42 seconds, the average charging current is halved. In general, the average charging current is: ICHRG = VDAC(Duty Ratio)/RSENSE Gated PFET Controller When using an external current regulator or current limited wall pack, simply remove the inductor L1 and catch diode D1. Set the DAC control bits VR1 = 1 and VR0 = 1, and select the desired duty ratio. By insuring that the voltage at the Sense pin is never greater than 140mV, the output of the integrator A1 will saturate high and the comparator A2 will never trip and turn the loop off. This can be achieved by removing the sense resistor and grounding the Sense pin or if the gas gauge is to be used, selecting RSENSE so that RSENSE /ICHRG < 140mV.
LTC1325
FUNCTIONAL DESCRIPTIO
Gas Gauge Mode Command: MOD1 = 1, MOD0 = 1, PS = 0 Status: BATP = X, BATR = X, FMCV = X, FEDV = X, FHTF = X, FLTF = X, t OUT = X
In the gas gauge mode, the average voltage across the sense resistor can be measured to determine the average battery load current. The output of the DAC is set to ground and switches S1, S3 and S4 are closed. A1 is configured as an inverting amplifier with R1 and R2 setting the gain to - 4. The voltage across the sense resistor is filtered by an RC circuit (RF, CF) amplified by A1, then converted by the ADC. The microprocessor can then accumulate the ADC measurements and do a time average to determine the total charge leaving the battery. The Sense pin voltage should not be more negative than - 450mV to ensure linearity. The RFCF circuit consists of an internal 1k resistor and an external capacitor connected to the Filter pin. RFCF should be longer than the measurement interval. With the serial clock running at 100kHz, it take 380s to shift in the command word and shift out the ADC measurement and status word. Trickle Resistor An external trickle resistor has several functions. First, it provides a continuous trickle charge current for topping off the battery and countering the effects of self-discharge. Second, it can be used to condition a deeply discharged battery for charging. The LTC1325 will not charge a battery unless its cell voltage is above 100mV (BATR). Finally, the resistor is required by the battery detect circuit to pull the VBAT pin high when the battery is removed. SERIAL INTERFACE The LTC1325 communicates with microprocessors and other external circuitry via a synchronous, half duplex, 4-wire serial interface. The clock CLK synchronizes the data transfer with each bit being transmitted on the falling edge and captured on the rising CLK edge in both transmitting and receiving systems. The LTC1325 first receives input data and then transmits back the A/D conversion result and status word (half duplex). Because of the half
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duplex operation, DIN and DOUT may be tied together allowing transmission over just three wires: CS, CLK and DATA (DIN/DOUT). Data transfer is initiated by a falling chip select CS signal. After CS falls, the LTC1325 looks for a start bit on DIN. The start bit is the first "logical one" clocked into the DIN input after CS goes low. The LTC1325 will ignore all leading zeros which precede this logical one. After the start bit is received, the 21 other control bits are shifted into the DIN pin to configure the LTC1325 and start a conversion. After the last command bit, the DOUT pin remains in three-state for one clock period before it is taken low for one null bit. Following the null bit, the conversion results and the 8 status bits are shifted out on the DOUT pin. At the end of the data exchange, CS should be brought high. MSB-First/LSB-First (MSBF Control Bit) The output data of the LTC1325 is programmed for MSBfirst or LSB-first sequence using the MSFB control bit. When MSBF = 1, data will appear on DOUT in MSB-first format. This is followed by the 8 status bits. Logical zeros will be filled in indefinitely following the last data bit to accommodate longer word lengths required by some microprocessors. When MSBF = 0, LSB-first data will follow the MSB-first data. Regardless of the state of MSBF, the status bits are always shifted out in the same order (see Figure 2). Accommodating Microprocessors with Different Word Lengths The LTC1325 will fill zeros indefinitely after the transmitted data until CS is brought high. At that time DOUT is disabled (three-stated). This makes for easy interfacing to MPU serial ports with different transfer increments including 4 bits (e.g., COP400) and 8 bits (e.g., SPI and MICROWIRE/PLUSTM). Any word length can be accommodated by the correct positioning of the start bit in the input word. Operation with DIN and DOUT Tied Together The LTC1325 can be operated with DIN and DOUT tied together. This eliminates one of the lines required to
MICROWIRE/PLUS is a trademark of National Semiconductor Corp.
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LTC1325
FUNCTIONAL DESCRIPTIO
communicate with the microprocessor. Data is transmitted in both directions on a single wire. The processor pin connected to this data line should be configurable as either an input or an output. The LTC1325 will take control of the data line and drive it low after the 23rd falling CLK edge after the start bit is received. Therefore the processor port must be switched to an input before this happens to avoid a conflict. Power-Up After Shutdown When a control word with the PS bit set to one is written to the LTC1325, it enters shutdown mode in which the VDD supply current is reduced to 30A. In this mode the onchip 3V regulator and all circuits powered off it are shut down. The only circuits that remain alive are DIN, CS and CLK input buffers. To take the LTC1325 out from shutdown mode, a high to low edge must be applied to the CS pin. Either DIN or CLK must be low when CS is low to prevent a false control word from being transmitted to the LTC1325. The 3V output decays with a time constant of 300ms with CREG = 4.7F. The microprocessor should wait three seconds before applying a wake-up edge to the CS pin to ensure proper power-up. TEMPERATURE SENSING NTC (Negative Temperature Coefficient) Thermistors The simplest method to sense temperature (battery or ambient) with an NTC thermistor is to use a voltage divider powered by the REG pin. This divider consists of a load resistor RL in series with a thermistor RT as shown in Figure 3. For a given thermistor, there is a value of RL which makes VDIV (T) linear over a narrow but adequate temperature range. The easiest method (Inflection Point Method) to calculate RL is to set the second temperature derivative of the divider output to 0. The equations relevant to this method are:
VDIV T VREG
( )=
1 =f T 1 + RL RT
()
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1 1 RT = exp - RTO T TO
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(2)
- 2 TO RL = RTO + 2 TO
T R = T O In T TO - T RTO
(3)
(4)
=
1 RT - T2
dRT dT
(5)
=
(6)
- 1 dVDIV = VDIV TO - + 2 dT TO 2 TO
()
(7)
where, VDIV (T) is the output of the divider, VREG is the voltage at the REG pin (3.072V nominal), RT is the thermistor resistance at some temperature T, RTO is the thermistor resistance at some reference temperature TO, is a constant dependent on thermistor material, is the temperature coefficient (in %/C) of RT at TO, and all temperatures are in K (i.e., TC + 273) There are two assumptions in the derivation of the above equations. is assumed to be constant and the temperature coefficient of RL is small compared to that of the thermistor. Most thermistor data sheets specify RTO, , RT/RTO ratios for two temperatures, , and tolerances for and RTO. Given , and RTO, it is easy to calculate RL from equation
(1)
LTC1325
APPLICATIONS INFORMATION
(3). Alternatively, may be calculated from the RT/RTO ratio using equation (4) or from , using equation (6). As a numerical example, consider the Panasonic ERT-D2FHL103S thermistor which has the following characteristics: 1. RT (25C) = RTO = 10k 2. = - 4.6%/C at TO = 25C 3. Ratio R25/R50 = 2.9 Using equation (4) and R25/R50 = 2.9, = (323 x 298)In (2.9)/(298 - 323) = 4099k. Alternatively, using equation (6) and = - 4.6%/C, = - (- 0.046)(298)2 = 4085k. Both values of are close to each other. Substituting = 4085k into equation (3) gives RL = 10k [4085 - (2 x 298)]/[4085 + (2 x 298)] = 7.45k. The nearest 1% resistor value is 7.5k. Figure 5 shows a plot of VDIV(T) measured at various temperatures for this thermistor with a 7.5k RL.
4.5 4.0
DIVIDER OUTPUT VOLTAGE (V)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 - 0.5 -60 -40
IDEAL ACTUAL
20 0 -20 40 TEMPERATURE (C)
60
80
LTC1325 * F05
Figure 5. ERT-D2FHL103S Divider
There are two methods of calculating battery or ambient temperature from ADC readings of the TBAT or TAMB channels. The first method is to store the VDIV(T) vs T curve as a lookup table. The second method is to use a straight line approximation. The equation of this line may be calculated from the slope dVDIV/dT at TO [see equation (7)] and assuming that the line passes through the point [TO, VDIV(TO)] on the curve. For the ERT-D2FHL103S, the slope is minus 34mV/C and the equation of the line is
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T = [2.605 - VDIV(T)]/0.034. The straight line approximation is accurate to within 2C over a temperature range of 5C to 45C, assuming 3% and 10% RTO tolerances. PTC (Positive Temperature Coefficient) Thermistors Positive Temperature Coefficient (PTC) thermistors may be used in battery chargers that do not require accurate temperature measurements. The resistance vs temperature characteristics of PTC exhibits a sharp increase at a selectable switch temperature TS. This sharp change is exploited in chargers which use TCO (Temperature Cutoff) or TCO (Difference between battery and ambient temperature). With TCO termination, a voltage divider consisting of a PTC and a low temperature coefficient load resistor is connected between REG and GND with the top end of the PTC at REG. The PTC is mounted on the battery to sense its temperature. The divider output is tied to TBAT. When the switch temperature is reached, the PTC resistance increases sharply causing TBAT to fall below HTF. This causes an HTF fault and charging is terminated. To implement TCO termination, the load resistor can, in principle, be replaced by a matching PTC and the divider now responds to differences between battery and ambient temperature. With both TCO and TCO terminations, the position of the battery temperature PTC can be swapped with the load resistor or ambient temperature PTC. In both cases, an LTF fault terminates charge when the trip point is reached. Note that in practice, matched PTCs are not readily available and for TCO termination, NTC thermistors are recommended. HARDWARE DESIGN PROCEDURE This section discusses the considerations in selecting each component of a simple battery charger (see Figures 3 and 4). Further applications assistance is provided in Application Note 64, using the LTC1325 Battery Management IC. 1. RSENSE: There are three factors in selecting RSENSE: a. LTC1325 VREF and Duty Ratio Settings b. Sense Resistor Dissipation c. ILOAD (RSENSE) < - 450mV for Gas Gauge Linearity
17
LTC1325
APPLICATIONS INFORMATION
The LTC1325 has five duty ratio and four VDAC settings giving 20 possible charge rates (for a given value of RSENSE) as shown in the following table. For any combination of VDAC and duty ratio, the average charging current is given by: AVG ICHRG = VDAC (Duty Ratio)/RSENSE
NORMALIZED VDAC 1 1(VR1 = 1, VR0 = 1) 1 1/3(VR1 = 1, VR0 = 0) 1/3 1/5(VR1 = 0, VR0 = 1) 1/5 1/10(VR1 = 0, VR0 = 0) 1/10 DUTY RATIO 1/2 1/4 1/8 1/2 1/4 1/8 1/6 1/12 1/24 1/10 l/20 1/40 1/20 1/40 1/80 1/16 1/16 1/48 1/80 1/160
Note that the table entries give relative charge rates assuming that the VR1 = 1, VR0 = 1, duty ratio = 1 entry is equivalent to a 1C charge rate. Therefore, the charge rate (in C-units) for other VR1, VR0, and duty ratio settings may be read directly from the table. In general, the VR1 = 1, VR0 = 1, duty ratio = 1 entry can be equivalent to any charge rate, say k times 1C. Then all entries in the table should be multiplied by k. In general, VDAC and duty ratio settings are changed by the microprocessor to charge batteries of different capacities or to alter charge rates when charging the same battery in several stages. For best accuracy, VR1 and VR0 should be set to 1 where possible. The power dissipation of the sense resistor varies between charge, discharge and gas gauge modes and should be calculated for all three modes. Typically, dissipation is higher in discharge and gas gauge modes since batteries can deliver higher currents than they can be charged with. In gas gauge mode, the load current supplied by the battery should not exceed 450mV/RSENSE for the gas gauge to remain linear in response. RSENSE should be low enough to ensure that ILOAD (RSENSE) does not fall below ground by more than 1 diode drop. 2. VDD Supply: VDD should be at least 1.8V above the maximum battery voltage to prevent a BATP = 0 error when the LTC1325 is in charge or discharge mode. If this requirement cannot be met in a specific application, an external battery divider should be connected
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between the VBAT and Sense pins and the internal divider should be set to divide-by-1. The minimum VDD supply must be greater than the end-of-charge voltage VEC times the number of cells (n) in the battery plus drops across the on-resistance of the PFET, inductor (VL), battery internal resistance RINT and sense resistor RSENSE. Minimum VDD should be the greater voltage of the results from these two equations: Min VDD = ICHRG [RDS(ON)(P1) + RSENSE + n(RINT)] + n(VEC) + VL or, Min VDD = n(VEC) + 1.8V Assuming VEC = 1.6V, the LTC1325 will charge up to 8 cells with a 16V supply. For a higher number of cells, an external level shifter and regulator are needed. In some applications, there are other circuits attached to the charging supply. When the charging supply (VDC) is powered down or removed, the battery may supply current to these circuits through the PFET body diode. To prevent this, a blocking diode can be added in series with VDC as shown in the circuit in the Typical Application section. 3. Inductor L: To minimize losses, the inductor should have low winding resistance. It should be able to handle expected peak charging currents without saturation. If the inductor saturates, the charging current is limited only by the total PFET RDS(ON), inductor winding resistance, RSENSE and VDD source resistance. This fault current may be high enough to damage the battery or cause the maximum power ratings of the PFET, inductor or RSENSE to be exceeded. 4. Catch Diode D1: The catch diode should have a low forward drop and fast reverse recovery time to minimize power dissipation. Total power loss is given by: PdD1 = VF (IF) + (VR)(f)(tRR)(IF)
LTC1325
APPLICATIONS INFORMATION
where, IF = forward diode current, IF = forward diode current just prior to turn off, VF = forward drop, VR = reverse diode voltage (approximately equal to VDD), f = PWM frequency (111kHz), and tRR = reverse recovery time The power and maximum reverse voltage ratings of the diode should be greater than PdD1 and VDD respectively. The catch diode should also have fast turn-on times to reduce the voltage glitch at its cathode when turning on. Schottky diodes have fast switching times and low forward drops and are recommended for D1. 5. Trickle Resistor RTRK: RTRK sets the desired trickle current in the battery to compensate for self-discharge which is in the order 1% and 2% of capacity per day for NiCd and NiMH batteries respectively. Trickle charge rates are typically in the C/30 to C/50 range, where C is battery capacity. ITRK = (VDD - VBAT)/RTRK where VBAT is the voltage of a full charged battery. Note that ITRK varies as the battery is being charged. 6. Thermistor RT and Load RL: The total resistance of the thermistor network should be greater than 30k at the high temperature extreme to minimize effects of load regulation (see REG pin loading). 7. Fault Setting Resistors R1, R2, R3 and R4: The voltage levels at the LTF, HTF and MCV pins are tapped from a resistor divider powered by the REG pin. The voltage levels are selected taking into account: a. Manufacturer Recommended Temperature and Voltage limits, b. Loading on the REG Pin (< 2mA) c. Input Voltage Ranges of the LTF, HTF and MCV Comparators: 1.6V < VLTF, VMCV < 2.8V and 0.5V < VHTF < 1.3V d. Thermistor Divider Temperature Curve Typical temperature limits for both NiCd and NiMH batteries are shown below.
BATTERY TYPE Standard Quick Fast or Rapid Trickle DISCHARGE TEMP RANGE (C) MIN - 20 - 20 - 20 - 20 MAX 45 to 50 45 to 50 45 to 50 45 to 50 CHARGE TEMP RANGE (C) MIN 0 10 15 0 MAX 45 to 50 45 to 50 45 to 50 45 to 50
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Note that the discharge limits are wider than the charge limits. To prolong battery life, manufacturers generally recommend discharge temperatures that are similar to the charge limits. For this reason, the LTC1325 recognizes the same LTF and HTF limits in both charge and discharge modes. MCV should be set just above the charging voltage per cell given in battery specifications. The voltage at the LTF and HTF pins should be set to correspond to narrowest temperature range. These are typically 15C and 45C. The corresponding voltages may be read from the thermistor divider temperature curve such as that shown in Figure 5. For this thermistor, it works out to be about for 2.12V for LTF and for 1.13V for HTF. The MCV may be conveniently tied to LTF since MCV is typically 2V. If desired, external analog switches under microprocessor control may be used to vary the LTF, HTF and MCV voltages between modes or for different charge rates. The values of R1, R2, R3 and R4 in Figure 3 can be calculated from the following equations: R4 = VHTF (RE/VREG) R3 = VMCV (RE - R4) R2 = VLTF (RE) - (R3 + R4) R1 = RE - (R2 + R3 + R4) where RE = R1 + R2 + R3 + R4 is chosen to minimize loading on the REG pin. A minimum value of 30k is recommended. Note that VLTF is assumed to be greater than VMCV. If this is not the case, VLTF and VMCV in the above equations should be swapped. If the MCV and LTF pins are shorted to the same point, R2 should be set to 0.
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LTC1325
APPLICATIONS INFORMATION
8. REG Pin Loading: The 3.072V regulator has a load regulation specification of - 5mV/mA. Since the ADC uses the same regulator as reference, it is desirable to reduce loading effects on the REG pin especially over temperature. Thermistors with RTO values of at least 10k at 25C are recommended. At 50C, the thermistor resistance could drop by a factor of 3 from its value at 25C. RL is chosen as explained in the section on Temperature Sensing. The temperature coefficient of RL is not critical since the thermistor tempco dominates the sensing circuit. 9. RDIS: RDIS is selected to limit the discharge current to a value within the battery discharge specifications and must have a power rating above IDIS2 (RDIS) where: IDIS = VBAT/[RDIS + RDS(ON)(N1)] 10. PFET(P1) and NFET(N1): For operation of the charge and discharge loops, VGS < VDD since the PGATE and DIS pins swing between 0 and VDD. VGS << VDD to minimize power dissipation. The power ratings of P1 and N1 should be above ICHRG2[RDS(ON)(P1)] and IDIS2 [RDS(ON)(N1)] respectively. VDS(MAX) should be above VDD. Charging from Supplies Above 16V In many applications, the charging supply is greater than the 16V maximum VDD rating of the LTC1325. The LTC1325 can easily be adapted to charge the batteries from a charging supply VDC that is above 16V by adding three external sub-circuits: 1. A regulator to drop VDC down to within the supply range of the LTC1325. 2. A level shifter between the PGATE and the gate of the PFET, P1, to ensure that P1 can be completely turned off when PGATE rises to VDD. 3. A voltage clamp on the VBAT pin to prevent RTRK from pulling VBAT above VDD. The Wide Voltage Battery Charger circuit in the Typical Application section shows low cost implementations of all three sub-circuits. C1, R11 and D4 generate a 15V VDD for the LTC1325. D3, R12 and C2 form a level shifter. The zener D3 is chosen to clamp the source gate voltage of the PFET to within the maximum gate source voltage rating of the latter. Finally, D2 clamps VBAT to 15V. Charging Batteries with Voltages Above 16V To charge a battery with a maximum (fully charged) voltage of above 16V, the charging supply VDC must be above 16V. Thus the charger will need the regulator, level shifter and clamp mentioned in the previous section. In addition, an external battery divider must be added to limit the voltage at the VBAT pin to less than VDD. This is shown in the typical application circuit, Wide Voltage Battery Charger. The resistors R9 and R10 are selected to divide the battery voltage by the number of cells in the battery and the battery divider internal to the LTC1325 is set to divide-by-1. The external divider prevents VBAT from ever rising to VDD and this causes the BATP (Battery Present Flag) to be high regardless of whether the battery is physically present or not. This does not affect the other operations of the LTC1325. SOFTWARE DESIGN A general charging algorithm consists of the following stages: Discharge Before Charge Fast Charge Top Off Charge Trickle Charge Under some operating and storage conditions, NiCd and NiMH batteries may not provide full capacity. In particular, repeated shallow charge and discharge cycles cause the "memory effect" in NiCd batteries. In order to restore full capacity (battery conditioning), these batteries have to be subjected to several deep discharge/charge cycles which will be provided by repetitions of the above algorithm. Figure 6 shows a simplified flowchart of a charging algorithm. In practice, this flowchart has to be augmented to take into account the occurrence of fail-safes at any point in the algorithm. For example, the battery temperature could rise above HTF during discharging or charging. General programming notes are as follows: 1. The start bit is always high. 2. The SGL/DIFF bit is generally set to low so that the ADC makes conversions with respect to ground.
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LTC1325
APPLICATIONS INFORMATION
3. The MSBF bit is set depending on whether the microprocessor clocks in serial data with MSB- or LSB-first. 4. The DS0 to DS2 bits can be anything except when entering idle mode or when requesting for ADC readings. In these cases, DS0 to DS2 are set to select the desired reading: TBAT, VCELL or TAMB. 5. The PS bit should always be 0 so that the LTC1325 does not go into shutdown mode. 6. The DR0 to DR2 should not select any of the test modes. It may assume different settings between Fast charge and Top Off charge in order to alter the charging current. 7. The FSCLR bit should be set to 1 to clear any faults and reset the timer when starting Discharge, Fast charge or Top Off. The status bits that the LTC1325 returns
START
NO
CONDITIONING? YES START DISCHARGE START TOP OFF CHARGE
WAIT
READ STATUS RESUME TOP OFF CHARGE EDV = 1? YES START FAST CHARGE NO WAIT
NO
RESUME FAST CHARGE
IDLE MODE AND WAIT
READ ADC AND STATUS
NO TERMINATE?
YES
Figure 6. Simple Charging Algorithm
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during the same I/O operation (that FSCLR is set to 1) should be checked to determine if faults were indeed cleared, i.e., discharging or charging has begun. This is not shown in the simplified flowchart of Figure 6. For commands other than the START commands, FSCLR should be set to 0 so as not to reset the timer. 8. The TO0 to TO2 bits should all be set to 1 in discharge mode to ensure discharge does not end prematurely due to a timeout fault. During Fast charge or Top Off charge, these bits are set to a value suitable for the charge rate used. For example, if the charge rate is 1C, the timeout period should be set to 80 minutes. 9. In charge mode, the CF capacitor filters the VCELL node and sees a small ripple due to ripple at the Sense pin. Prior to taking an ADC reading, the LTC1325 is put in
WAIT
IDLE MODE
READ ADC AND STATUS
TERMINATE? YES IDLE MODE AND WAIT
MORE CONDITIONING? NO END
YES
LTC1325 * F06
21
LTC1325
APPLICATIONS INFORMATION
idle mode to minimize noise. The microprocessor should either disregard readings or wait for a second or so before taking a reading. This is to allow VCELL to decay to the correct cell voltage. The worst case time constant is 150k(CF ). 10. Prior to the first START command, the battery divider setting may be incorrect so that CF may charge to a voltage that causes EDV, BATR or MCV faults. The worst case time constant is as in (9). The microprocessor should check faults during the transmission of a START command and resend the START command again when CF has been given enough time to charge up to the correct value. MICROPROCESSOR INTERFACES The LTC1325 can interface directly to either synchronous, serial or parallel I/O ports of most popular microprocessors. With a parallel port, 3 or 4 I/O lines can be programmed to form a serial link to the LTC1325. Motorola SPI (68HC11) The 68HC11 has a dedicated synchronous serial interface called the Serial Peripheral Interface (SPI) which transfers data with MSB-first and in 8-bit increments. To communicate with this microprocessor, the LTC1325 MSBF control bit should be set to 1. The SPI has four lines: Master In Slave Out (MISO), Master Out Slave In (MOSI), Serial Clock (SCK) and Slave Select (SS). The 68HC11 is configured as a Master by tying the SS line high. A control byte is written to the Serial Peripheral Control Register (SPCR) to select master mode, set baud rate and clock timing relationship. Another byte is written to the Port D Direction Register (DDRD) to set MOSI, SCK and bit 0 (CS of LTC1325) as outputs. The 68HC11 clocks in data from the LTC1325 simultaneously under the control of SCK. The microprocessor transmits the LTC1325 command word in 4 bytes. This is followed by 2 more dummy bytes (with all bits set low) in order to clock in the remaining LTC1325 ADC and status bits. This software example allows you to verify communications with the LTC1325. The command word configures the LTC1325 to perform an A/D conversion on the general purpose VIN input. VIN can be tied to GND or REG or to a wiper on a potentiometer between these two. Table 1 illustrates a complete 6-byte exchange. Note that the first byte is padded with zeroes to align the A/D data and status with byte boundaries. SPCR = (SPIE = 0, SPE = 1, DWOM = 0, MSTR = 1, CPOL = 0, CPHA = 0, SPR1 = 0, SPR0 = 1) DDRD = (BIT7 = 0, BIT6 = 0, DDR5 = 1, DDR4 = 1, DDR3 = 1, DDR2 = 0, DDR1 = 0, DDR0 = 1)
Table 1. 6-Byte Exchange SPI Communication with LTC1325
5V 68HC11 SS SCK MOSI PORTD.0 MISO LTC1325 CLK DIN CS DOUT
22
U
W
U
U
0
0
0
0
0
0
START MOD0
BYTE #1 TX
X
X
X
X
X
X
X
X
BYTE #1 RX
MOD1
SGL/ DIFF
MSBF
DS0
DS1
DS2
DIV0
DIV1
BYTE #2 TX
X
X
X
X
X
X
X
X
BYTE #2 RX
DIV2
DIV3
PS
DR0
DR1
DR2
FSCLR
TO0
BYTE #3 TX
X
X
X
X
X
X
X
X
BYTE #3 RX
TO1
TO2
VR0
VR1
0
0
0
0
BYTE #4 TX
X
X
X
X
X
0
D9
D8
BYTE #4 RX
X
X
X
X
X
X
X
X
BYTE #5 TX
D7
D6
D5
D4
D3
D2
D1
D0
BYTE #5 RX
X
X
X
X
X
X
X
X
BYTE #6 TX
BATP
BATR
FMCV
FEVD
FHTF
FLTF
t0UT
FS
BYTE #6 RX
X = DON'T CARE
LTC1325 * AI01
LTC1325
APPLICATIONS INFORMATION
LABEL MNEMONIC OPERAND
LDAA STAA LDAA STAA LDX BCLR LDAA STAA TST BPL LDAA STAA TST BPL LDAA STAA TST BPL LDAA STAA #$51 $1028 #$39 $1009 #$1000 $08,X,#$01 #$02 $102A $1029 LOOP1 #$24 $102A $1029 LOOP2 #$03 $102A $1029 LOOP3 #$C0 $102A
COMMENTS
Write control byte to the SPCR Setup Port D DDRD Port D Bit 0 is CS Load port base ADDR Take CS low Send Byte #1 (MSB) with START bit Check for SPI transfer complete bit Send Byte 2 Check for SPI transfer complete bit Send Byte 3 Check for SPI transfer complete bit Send Byte 4
CSLOW
LOOP1
LOOP2
LOOP3
TYPICAL APPLICATION
Wide Voltage Battery Charger
VDC 25V MBR320 NOTE 7 D3 1N4740A R12 100k P1 IRF9Z30 C2 0.1F L1 62H
NOTE 1 NOTE 2
R11 220 1/2W
C1 1F
+
D4 1N4744A 15V
MPU (e.g. 8051) p1.4 p1.3 p1.2 R1
REG DOUT DIN CS CLK LTF MCV HTF GND
VDD PGATE DIS VBAT TBAT TAMB VIN SENSE FILTER NOTE 6 THERM 2 R5 THERM 1 R7 C3 500pF C5 0.1F R14 100 NOTE 5 R9 NOTE 1 NOTE 4 N1 IRF830 D2 1N4744A 15V RSENSE R13 R6 RDIS
CREG 4.7F
+
R2
R3
LTC1325 CF 1F
R4
NOTE 1: NEEDED WHEN VDC > 16V OR MAXIMUM BATTERY VOLTAGE, VBAT > 16V. NOTE 2: REGULATOR. OMIT THIS BLOCK AND SHORT VDD TO VDC WHEN VDC < 16V. NOTE 3: LEVEL SHIFTER. OMIT THIS BLOCK AND SHORT PGATE TO P1 GATE WHEN VDC < 16V.
NOTE 4: ZENER TO CLAMP VBAT TO BELOW VDD. OMIT WHEN VDC < 16V. NOTE 5: EXTERNAL BATTERY DIVIDER. NEEDED WHEN MAXIMUM BATTERY VOLTAGE, VBAT > 16V. NOTE 6: VIN IS AN UNCOMMITTED A/D CHANNEL.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
W
U
U
U
LABEL MNEMONIC OPERAND
LOOP4 TST BPL LDAA ANDA STAA LDAA STAA LOOP5 TST BPL LDAA STAA LDAA STAA LOOP6 TST BPL LDAA STAA BSET BRA $1029 LOOP4 $102A #$03 HIDATA #$00 $102A $1029 LOOP5 $102A LODATA #$00 $102A $1029 LOOP6 $102A STATUS $08,X,#$01 CSLOW
COMMENTS
Check for SPI transfer complete bit Get A/D high byte Mask off unwanted bits Store in user memory Send dummy Byte #1 Check for SPI transfer complete bit Get A/D low byte Store in user memory Send dummy Byte #2 Check for SPI transfer complete bit Get STATUS byte Store in user memory Raise CS high Loop for continuous readings
NOTE 1 NOTE 3
D1 1N5818 RTRK
+ C4
22F VBAT R8 100
R10
NOTE 7: OPTIONAL DIODE TO PREVENT BATTERY DRAIN WHEN THE CHARGING SUPPLY IS POWERED DOWN (SEE SECTION 2, HARDWARE DESIGN PROCEDURE).
1325 TA02
23
LTC1325
PACKAGE DESCRIPTION U
Dimension in inches (millimeters) unless otherwise noted. N Package 18-Lead Plastic DIP
0.300 - 0.325 (7.620 - 8.255) 0.130 0.005 (3.302 0.127) 0.015 (0.381) MIN 0.045 - 0.065 (1.143 - 1.651) 18 17 16 15 0.900* (22.860) MAX 14 13 12 11 10
0.009 - 0.015 (0.229 - 0.381)
0.065 0.255 0.015* (1.651) (6.477 0.381) TYP 0.125 (3.175) MIN 0.018 0.003 (0.457 0.076) 1 2 3 4 5 6 7 8 9
0.005 (0.127) MIN 0.100 0.010 (2.540 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
N18 0695
S Package 18-Lead Plastic SOL
0.447 - 0.463* (11.354 - 11.760) 18 0.291 - 0.299** (7.391 - 7.595)
0.010 - 0.029 x 45 (0.254 - 0.737)
17
16
15
14
13
12
11
10
0.093 - 0.104 (2.362 - 2.642)
0.037 - 0.045 (0.940 - 1.143)
0 - 8 TYP
SEE NOTE
0.394 - 0.419 (10.007 - 10.643)
0.009 - 0.013 (0.229 - 0.330)
NOTE 1
0.050 (1.270) TYP
0.004 - 0.012 (0.102 - 0.305) 1 2 3 4 5 6 7 8 9
SW18 0695
0.016 - 0.050 (0.406 - 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.014 - 0.019 (0.356 - 0.482) TYP
RELATED PARTS
PART NUMBER
LT 1510 LT1512
(R)
DESCRIPTION
Constant Voltage/Constant Current Battery Charger SEPIC Constant Current/Constant Voltage Battery Charger
COMMENTS
1.3A, Li-Ion, NiCd, NiMH, Pb-Acid Charger 0.75A, VIN Greater or Less Than VBAT
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
LT/GP 0895 2K REV A * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1994

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